/*-------------------------------------------------------------------------- LEDCore211.H (ver 0.1) Header file for the GenCore Turbo LEDCore211.H Copyright (c) 2003-2011 CORERIVER Semiconductor. All rights reserved. --------------------------------------------------------------------------*/ #ifndef LEDC211_HEADER_FILE #define LEDC211_HEADER_FILE 1 /*------------------------------------------------ Byte Registers ------------------------------------------------*/ sfr P0 = 0x80; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr ALTSEL2 = 0x84; sfr ALTSEL = 0x85; sfr CKSEL = 0x86; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr CKCON = 0x8E; sfr RINGCON = 0x8F; sfr EXIF = 0x91; sfr P2 = 0xA0; sfr IE = 0xA8; sfr SYSCON = 0xAA; sfr LDOCON = 0xAB; sfr INTSEL = 0xB2; sfr IP = 0xB8; sfr LVDCON = 0xBB; sfr TSCON = 0xC1; sfr TSCFG = 0xC2; sfr TSPDH = 0xC3; sfr PMR = 0xC4; sfr STATUS = 0xC5; sfr OSCICN = 0xC6; sfr TSOSCICN = 0xC7; sfr TSPDM = 0xC9; sfr TSPDL = 0xCA; sfr TSPCH = 0xCB; sfr TSPCM = 0xCC; sfr TSPCL = 0xCD; sfr TSENCTH = 0xCE; sfr TSENCTL = 0xCF; sfr PSW = 0xD0; sfr P0SEL = 0xD1; sfr P2SEL = 0xD3; sfr WDCON = 0xD8; sfr P0TYP = 0xD9; sfr P2TYP = 0xDB; sfr ACC = 0xE0; sfr P0DIR = 0xE1; sfr P2DIR = 0xE3; sfr I2C0ST = 0xE8; sfr I2C0CON = 0xE9; sfr I2C0CFG = 0xEA; sfr I2C0SLA = 0xEB; sfr I2C0DAT = 0xEC; sfr P0HD = 0xEE; sfr B = 0xF0; sfr EECNTLD = 0xF1; sfr EECNTL = 0xF2; sfr EECNTM = 0xF3; sfr EECON = 0xF6; sfr EEAEN = 0xF7; sfr I2C1ST = 0xF8; sfr I2C1CON = 0xF9; sfr I2C1CFG = 0xFA; sfr I2C1SLA = 0xFB; sfr I2C1DAT = 0xFC; /*------------------------------------------------ P0 (80h) Bit Register ------------------------------------------------*/ sbit P0_0 = 0x80; sbit P0_1 = 0x81; sbit P0_2 = 0x82; sbit P0_3 = 0x83; sbit P0_4 = 0x84; sbit P0_5 = 0x85; sbit P0_6 = 0x86; sbit P0_7 = 0x87; /*------------------------------------------------ TCON (88h) Bit Register ------------------------------------------------*/ sbit IT0 = 0x88; // External interrupt 0 level/edge trigger control (Edge detect(IT0=1)/Level detect(IT0=0;default)) sbit IE0 = 0x89; // External interrupt 0 flag sbit TR0 = 0x8C; // Timer 0 run control sbit TF0 = 0x8D; // Timer 0 overflow flag sbit TR1 = 0x8E; // Timer 1 run control sbit TF1 = 0x8F; // Timer 1 overflow flag /*------------------------------------------------ P2 (A0h) Bit Register ------------------------------------------------*/ sbit P2_0 = 0xA0; sbit P2_1 = 0xA1; sbit P2_2 = 0xA2; /*------------------------------------------------ IE (A8) Bit Register ------------------------------------------------*/ sbit EX0 = 0xA8; sbit ET0 = 0xA9; sbit EWDT = 0xAA; sbit ET1 = 0xAB; sbit EI2C0 = 0xAC; sbit EI2C1 = 0xAD; sbit ETS = 0xAE; sbit EA = 0xAF; /*------------------------------------------------ IP (B8h) Bit Register ------------------------------------------------*/ sbit PX0 = 0xB8; sbit PT0 = 0xB9; sbit PWDT = 0xBA; sbit PT1 = 0xBB; sbit PI2C0 = 0xBC; sbit PI2C1 = 0xBD; sbit PTS = 0xBE; /*------------------------------------------------ PSW (D0h) Bit Register ------------------------------------------------*/ sbit p = 0xD0; // Parity bit. Set/clear by H/W according to ACC odd parity sbit F1 = 0xD1; // User flag 1 sbit OV = 0xD2; // Overflow flag sbit RS0 = 0xD3; // Register bank select [0,0]Bank0, [0,1]Bank1 sbit RS1 = 0xD4; // Register bank select [1,0]Bank2, [1,1]Bank3 sbit F0 = 0xD5; // User flag 0 sbit AC = 0xD6; // Auxiliary carry flag sbit CY = 0xD7; // Carry flag /*------------------------------------------------ WDCON (D8h) Bit Register ------------------------------------------------*/ sbit RWT = 0xD8; // Restart Watchdog Timer sbit EWT = 0xD9; // Watchdog Timer Reset Enable sbit WTRF = 0xDA; // Watchdog Timer Reset Flag. Only cleared by S/W sbit WDIF = 0xDB; // Watchdog Timer Interrupt Flag sbit PFI = 0xDC; // Poser-Fail interrupt Flag (always 1 @ 3V operation) sbit EPFI = 0xDD; // Enable Poser-fail Interrupt sbit POR = 0xDE; // Power-on Reset Flag sbit WDMOD = 0xDF; // WDT mode selection flag /*------------------------------------------------ ACC (E0h) Bit Register ------------------------------------------------*/ sbit ACC0 = 0xE0; sbit ACC1 = 0xE1; sbit ACC2 = 0xE2; sbit ACC3 = 0xE3; sbit ACC4 = 0xE4; sbit ACC5 = 0xE5; sbit ACC6 = 0xE6; sbit ACC7 = 0xE7; /*------------------------------------------------ I2C0ST (E8h) Bit Register I2C1ST (F8h) Bit Register ------------------------------------------------*/ sbit I2CBF = 0xE8; // Busy flag in slave&master mode // [0]RX not complete(Receive), TX not complete(Transmitter) // [1]RX complite(Recieve), TX complite(Transmitter) sbit I2CS = 0xE9; // Start flag in slave&master mode // [0]Indicates Start bit was not detected // [1]Indecates Start bit was detected sbit I2CP = 0xEA; // Stop flag in slave&master mode // [0]Indicates Stop bit was not detected // [1]Indicates Stop bit was detected sbit I2CDA = 0xEB; // Data/Address flag in slave mode // [0]Indecates the last byte received or transmitted was Data // [1]Indecates the last byte received or transmitted was Address sbit I2CRW = 0xEC; // I2C Read/Write flag in slave mode // [0]Write state, [1]Read state sbit I2CACK = 0xED; // I2C Acknowledge flag in slave&master mode // [0]Indicate receiving Acknowledge bit // [1]Indecate receiving Not Acknwledge bit sbit I2COF = 0xEE; // I2C Overflow Flag in slave&master // [0]Idle, [1]Overflow occurred sbit I2CIF = 0xEF; // I2C Master Interrupt Flag in slave&master mode // [0]Idel, [1]Interrupt occurred /*------------------------------------------------ B (F0h) Bit Register ------------------------------------------------*/ sbit B0 = 0xF0; sbit B1 = 0xF1; sbit B2 = 0xF2; sbit B3 = 0xF3; sbit B4 = 0xF4; sbit B5 = 0xF5; sbit B6 = 0xF6; sbit B7 = 0xF7; /*------------------------------------------------ P0 (80h) Bit Register ------------------------------------------------*/ #define P0_0_ 0x01 #define P0_1_ 0x02 #define P0_2_ 0x04 #define P0_3_ 0x08 #define P0_4_ 0x10 #define P0_5_ 0x20 #define P0_6_ 0x40 #define P0_7_ 0x80 /*------------------------------------------------ SP (81h) Bit Register ------------------------------------------------*/ #define SP0_ 0x01 #define SP1_ 0x02 #define SP2_ 0x04 #define SP3_ 0x08 #define SP4_ 0x10 #define SP5_ 0x20 #define SP6_ 0x40 #define SP7_ 0x80 /*------------------------------------------------ DPL (82h) Bit Register ------------------------------------------------*/ #define DPL0_ 0x01 #define DPL1_ 0x02 #define DPL2_ 0x04 #define DPL3_ 0x08 #define DPL4_ 0x10 #define DPL5_ 0x20 #define DPL6_ 0x40 #define DPL7_ 0x80 /*------------------------------------------------ DPH (83h) Bit Register ------------------------------------------------*/ #define DPH0_ 0x01 #define DPH1_ 0x02 #define DPH2_ 0x04 #define DPH3_ 0x08 #define DPH4_ 0x10 #define DPH5_ 0x20 #define DPH6_ 0x40 #define DPH7_ 0x80 /*------------------------------------------------ ALTSEL2 (84h) Bit Register ------------------------------------------------*/ #define I2C0_A_ 0x02 #define ISP_DIS_ 0x04 /*------------------------------------------------ ALTSEL (85h) Bit Register ------------------------------------------------*/ #define RST_IOEN_ 0x01 #define XTAL_IOEN_ 0x02 /*------------------------------------------------ CKSEL (86h) Bit Register ------------------------------------------------*/ #define R32KEN_ 0x01 #define RGPR_ 0x02 #define TS_XTRG_ 0x04 #define R24MOE_ 0x08 #define R32KOE_ 0x10 /*------------------------------------------------ PCON (87h) Bit Values ------------------------------------------------*/ #define IDL_ 0x01 #define PD_ 0x02 #define GF0_ 0x04 #define GF1_ 0x08 #define POF_ 0x10 #define SMOD0_ 0x40 #define SMOD1_ 0x80 /*------------------------------------------------ TCON (88h)Bit Register ------------------------------------------------*/ #define IT0_ 0x01 #define IE0_ 0x02 #define TR0_ 0x10 #define TF0_ 0x20 #define TR1_ 0x40 #define TF1_ 0x80 /*------------------------------------------------ TMOD (89h) Bit Values ------------------------------------------------*/ #define M0_ 0x01 #define M1_ 0x02 #define CT0_ 0x04 #define GATE0_ 0x08 #define M2_ 0x10 #define M3_ 0x20 #define CT1_ 0x40 #define GATE1_ 0x80 /*------------------------------------------------ TL0 (8Ah) Bit Register ------------------------------------------------*/ #define TL0_0_ 0x01 #define TL0_1_ 0x02 #define TL0_2_ 0x04 #define TL0_3_ 0x08 #define TL0_4_ 0x10 #define TL0_5_ 0x20 #define TL0_6_ 0x40 #define TL0_7_ 0x80 /*------------------------------------------------ TL1 (8Bh) Bit Register ------------------------------------------------*/ #define TL1_0_ 0x01 #define TL1_1_ 0x02 #define TL1_2_ 0x04 #define TL1_3_ 0x08 #define TL1_4_ 0x10 #define TL1_5_ 0x20 #define TL1_6_ 0x40 #define TL1_7_ 0x80 /*------------------------------------------------ TH0 (8Ch) Bit Register ------------------------------------------------*/ #define TH0_0_ 0x01 #define TH0_1_ 0x02 #define TH0_2_ 0x04 #define TH0_3_ 0x08 #define TH0_4_ 0x10 #define TH0_5_ 0x20 #define TH0_6_ 0x40 #define TH0_7_ 0x80 /*------------------------------------------------ TH1 (8Dh) Bit Register ------------------------------------------------*/ #define TH1_0_ 0x01 #define TH1_1_ 0x02 #define TH1_2_ 0x04 #define TH1_3_ 0x08 #define TH1_4_ 0x10 #define TH1_5_ 0x20 #define TH1_6_ 0x40 #define TH1_7_ 0x80 /*------------------------------------------------ CKCON (8Eh) Bit Register ------------------------------------------------*/ #define T0M_ 0x04 #define T1M_ 0x08 #define WD0_ 0x20 #define WD1_ 0x40 #define WD2_ 0x80 /*------------------------------------------------ RINGCON (8Fh) Bit Register ------------------------------------------------*/ #define RINGC0_ 0x01 #define RINGC1_ 0x02 #define RINGC2_ 0x04 #define RINGC3_ 0x08 #define RINGC4_ 0x10 #define RINGC5_ 0x20 #define RINGC6_ 0x40 #define RINGC7_ 0x80 /*------------------------------------------------ EXIF (91h) Bit Register ------------------------------------------------*/ #define BGS_ 0x01 /* Band-gap Select. When set, LVD will run in power-down mode. */ #define RGSL_ 0x02 /* When wakeup from power down mode in XTAL clock, use RING oscillator as system clock during 65,536 XTAL clocks */ #define RGMD_ 0x04 /* RING mode */ #define XTRG_ 0x08 /* Crystal Select. Read only*/ /*------------------------------------------------ P2 (A0h) Bit Register ------------------------------------------------*/ #define P2_0_ 0x01 #define P2_1_ 0x02 #define P2_2_ 0x04 /*------------------------------------------------ IE (A8h) Bit Register ------------------------------------------------*/ #define EX0_ 0x01 #define ET0_ 0x02 #define EWDT_ 0x04 #define ET1_ 0x08 #define EI2C0_ 0x10 #define EI2C1_ 0x20 #define ETS_ 0x40 #define EA_ 0x80 /*------------------------------------------------ INTSEL (A9h) Bit Register ------------------------------------------------*/ #define INT0EN_ 0x01 #define INT1EN_ 0x02 #define INT2EN_ 0x04 #define INT3EN_ 0x08 /*------------------------------------------------ SYSCON (AAh) Bit Register ------------------------------------------------*/ #define SWRST_ 0x01 /*------------------------------------------------ LDOCON (ABh) Bit Register ------------------------------------------------*/ #define TUNE0_ 0x01 #define TUNE1_ 0x02 #define TUNE2_ 0x04 #define TUNE3_ 0x08 #define LDO_ON_ 0x10 /*------------------------------------------------ IPH (B7h) Bit Register ------------------------------------------------*/ #define PX0H_ 0x01 #define PT0H_ 0x02 #define PWDTH_ 0x04 #define PT1H_ 0x08 #define PI2C0H_ 0x10 #define PI2C1H_ 0x20 #define PTSH_ 0x40 /*------------------------------------------------ IP (B8h) Bit Register ------------------------------------------------*/ #define PX0_ 0x01 #define PT0_ 0x02 #define PWDT_ 0x04 #define PT1_ 0x08 #define PI2C0_ 0x10 #define PI2C1_ 0x20 #define PTS_ 0x40 /*------------------------------------------------ LVDCON (BBh) Bit Register ------------------------------------------------*/ #define PFI27_ 0x01 #define PFISEL_ 0x02 /*------------------------------------------------ TSCON (C1h) Bit Register ------------------------------------------------*/ #define TS_RUN_ 0x01 #define TSIF_ 0x02 #define TS_CNT_CLR_ 0x04 /*------------------------------------------------ TSCFG (C2h) Bit Register ------------------------------------------------*/ #define TSSHIFT0_ 0x01 #define TSSHIFT1_ 0x02 #define TSDRV0_ 0x04 #define TSDRV1_ 0x08 #define TSDRV2_ 0x10 /*------------------------------------------------ TSPDH (C3h)Bit Register ------------------------------------------------*/ #define TSPD16_ 0x01 #define TSPD17_ 0x02 #define TSPD18_ 0x04 #define TSPD19_ 0x08 #define TSPD20_ 0x10 #define TSPD21_ 0x20 #define TSPD22_ 0x40 #define TSPD23_ 0x80 /*------------------------------------------------ PMR (C4h)Bit Register ------------------------------------------------*/ #define XTOFF_ 0x08 /*------------------------------------------------ STATUS (C5h)Bit Register ------------------------------------------------*/ #define XTUP_ 0x10 /*------------------------------------------------ OSCICN (C6h)Bit Register ------------------------------------------------*/ #define DIV0_ 0x01 #define DIV1_ 0x02 #define RINGON_ 0x04 #define DIV2_ 0x08 /*------------------------------------------------ TSOSCICN (C7h)Bit Register ------------------------------------------------*/ #define TSRDIV0_ 0x01 #define TSRDIV1_ 0x02 #define TSRINGON_ 0x04 /*------------------------------------------------ TSPDM (C9h)Bit Register ------------------------------------------------*/ #define TSPD8_ 0x01 #define TSPD9_ 0x02 #define TSPD10_ 0x04 #define TSPD11_ 0x08 #define TSPD12_ 0x10 #define TSPD13_ 0x20 #define TSPD14_ 0x40 #define TSPD15_ 0x80 /*------------------------------------------------ TSPDL (CAh) Bit Register ------------------------------------------------*/ #define TSPD0_ 0x01 #define TSPD1_ 0x02 #define TSPD2_ 0x04 #define TSPD3_ 0x08 #define TSPD4_ 0x10 #define TSPD5_ 0x20 #define TSPD6_ 0x40 #define TSPD7_ 0x80 /*------------------------------------------------ TSPCH (CBh) Bit Register ------------------------------------------------*/ #define TSPC16_ 0x01 #define TSPC17_ 0x02 #define TSPC18_ 0x04 #define TSPC19_ 0x08 #define TSPC20_ 0x10 #define TSPC21_ 0x20 #define TSPC22_ 0x40 #define TSPC23_ 0x80 /*------------------------------------------------ TSPCM (CCh) Bit Register ------------------------------------------------*/ #define TSPC8_ 0x01 #define TSPC9_ 0x02 #define TSPC10_ 0x04 #define TSPC11_ 0x08 #define TSPC12_ 0x10 #define TSPC13_ 0x20 #define TSPC14_ 0x40 #define TSPC15_ 0x80 /*------------------------------------------------ TSPCL (CDh) Bit Register ------------------------------------------------*/ #define TSPC0_ 0x01 #define TSPC1_ 0x02 #define TSPC2_ 0x04 #define TSPC3_ 0x08 #define TSPC4_ 0x10 #define TSPC5_ 0x20 #define TSPC6_ 0x40 #define TSPC7_ 0x80 /*------------------------------------------------ TSENCTH (CEh) Bit Register ------------------------------------------------*/ #define TSENC8_ 0x01 #define TSENC9_ 0x02 #define TSENC10_ 0x04 #define TSENC11_ 0x08 #define TSENC12_ 0x10 #define TSENC13_ 0x20 #define TSENC14_ 0x40 #define TSENC15_ 0x80 /*------------------------------------------------ TSENCTL (CFh) Bit Register ------------------------------------------------*/ #define TSENC0_ 0x01 #define TSENC1_ 0x02 #define TSENC2_ 0x04 #define TSENC3_ 0x08 #define TSENC4_ 0x10 #define TSENC5_ 0x20 #define TSENC6_ 0x40 #define TSENC7_ 0x80 /*------------------------------------------------ PSW (D0h) Bit Register ------------------------------------------------*/ #define P_ 0x01 #define F1_ 0x02 #define OV_ 0x04 #define RS0_ 0x08 #define RS1_ 0x10 #define F0_ 0x20 #define AC_ 0x40 #define CY_ 0x80 /*------------------------------------------------ P0SEL (D1h) Bit Register ------------------------------------------------*/ #define P0SEL_0_ 0x01 #define P0SEL_1_ 0x02 #define P0SEL_2_ 0x04 #define P0SEL_3_ 0x08 #define P0SEL_4_ 0x10 #define P0SEL_5_ 0x20 #define P0SEL_6_ 0x40 #define P0SEL_7_ 0x80 /*------------------------------------------------ P2SEL (D3h) Bit Register ------------------------------------------------*/ #define P2SEL_0_ 0x01 #define P2SEL_1_ 0x02 #define P2SEL_2_ 0x04 /*------------------------------------------------ WDCON (D8h) Bit Register ------------------------------------------------*/ #define RWT_ 0x01 #define EWT_ 0x02 #define WTRF_ 0x04 #define WDIF_ 0x08 #define PFI_ 0x10 #define EPFI_ 0x20 #define POR_ 0x40 #define WDMOD_ 0x80 /*------------------------------------------------ P0TYPE (D9h) Bit Register ------------------------------------------------*/ #define P0TYPE_0_ 0x01 #define P0TYPE_1_ 0x02 #define P0TYPE_2_ 0x04 #define P0TYPE_3_ 0x08 #define P0TYPE_4_ 0x10 #define P0TYPE_5_ 0x20 #define P0TYPE_6_ 0x40 #define P0TYPE_7_ 0x80 /*------------------------------------------------ P2TYPE (DBh) Bit Register ------------------------------------------------*/ #define P2TYPE_0_ 0x01 /*------------------------------------------------ ACC (E0h)Bit Register ------------------------------------------------*/ #define ACC0_ 0x01 #define ACC1_ 0x02 #define ACC2_ 0x04 #define ACC3_ 0x08 #define ACC4_ 0x10 #define ACC5_ 0x20 #define ACC6_ 0x40 #define ACC7_ 0x80 /*------------------------------------------------ P0DIR (E1h) Bit Register ------------------------------------------------*/ #define P0DIR_0_ 0x01 #define P0DIR_1_ 0x02 #define P0DIR_2_ 0x04 #define P0DIR_3_ 0x08 #define P0DIR_4_ 0x10 #define P0DIR_5_ 0x20 #define P0DIR_6_ 0x40 #define P0DIR_7_ 0x80 /*------------------------------------------------ P2DIR (E3h) Bit Register ------------------------------------------------*/ #define P2DIR_0_ 0x01 /*------------------------------------------------ I2C0ST (E8h) Bit Register I2C1ST (F8h) Bit Register ------------------------------------------------*/ #define I2CBF_ 0x01 #define I2CS_ 0x02 #define I2CP_ 0x04 #define I2CDA_ 0x08 #define I2CRW_ 0x10 #define I2CACK_ 0x20 #define I2COF_ 0x40 #define I2CIF_ 0x80 /*------------------------------------------------ I2C0CON (E9h) Bit Register I2C1CON (F9h) Bit Register ------------------------------------------------*/ #define I2CEN_ 0x01 #define I2CIOEN_ 0x02 #define SCLHD_ 0x20 #define SLA2ME_ 0x40 /*------------------------------------------------ I2C0CFG (EAh) Bit Register I2C1CFG (FAh) Bit Register ------------------------------------------------*/ #define GCE_ 0x01 #define SPIE_ 0x02 #define ADSEL_ 0x04 /*------------------------------------------------ I2C0SLA (EBh) Bit Register ------------------------------------------------*/ #define SLA0_0_ 0x01 #define SLA0_1_ 0x02 #define SLA0_2_ 0x04 #define SLA0_3_ 0x08 #define SLA0_4_ 0x10 #define SLA0_5_ 0x20 #define SLA0_6_ 0x40 #define SLA0_7_ 0x80 /*------------------------------------------------ I2C0DAT (ECh) Bit Register ------------------------------------------------*/ #define MDAT0_0_ 0x01 #define MDAT0_1_ 0x02 #define MDAT0_2_ 0x04 #define MDAT0_3_ 0x08 #define MDAT0_4_ 0x10 #define MDAT0_5_ 0x20 #define MDAT0_6_ 0x40 #define MDAT0_7_ 0x80 /*------------------------------------------------ P0HD (EEh) Bit Register ------------------------------------------------*/ #define P0HD0_ 0x01 #define P0HD1_ 0x02 #define P0HD2_ 0x04 #define P0HD3_ 0x08 #define P0HD4_ 0x10 #define P0HD5_ 0x20 #define P0HD6_ 0x40 #define P0HD7_ 0x80 /*------------------------------------------------ B (F0h) Bit Value ------------------------------------------------*/ #define B0_ 0x01 #define B1_ 0x02 #define B2_ 0x04 #define B3_ 0x08 #define B4_ 0x10 #define B5_ 0x20 #define B6_ 0x40 #define B7_ 0x80 /*------------------------------------------------ EECNTLD (F1h) Bit Register ------------------------------------------------*/ #define EECNTLD_ 0x80 /*------------------------------------------------ EECNTL (F2h) Bit Value ------------------------------------------------*/ #define EECNT0_ 0x01 #define EECNT1_ 0x02 #define EECNT2_ 0x04 #define EECNT3_ 0x08 #define EECNT4_ 0x10 #define EECNT5_ 0x20 #define EECNT6_ 0x40 #define EECNT7_ 0x80 /*------------------------------------------------ EECNTM (F3h) Bit Value ------------------------------------------------*/ #define EECNT8_ 0x01 #define EECNT9_ 0x02 #define EECNT10_ 0x04 #define EECNT11_ 0x08 #define EECNT12_ 0x10 #define EECNT13_ 0x20 #define EECNT14_ 0x40 #define EECNT15_ 0x80 /*------------------------------------------------ EECON (F6h) Bit Value ------------------------------------------------*/ #define EINIT_ 0x01 #define EWST_ 0x02 #define ECOMM_ 0x04 #define EWF_ 0x08 #define EDONE_ 0x10 #define EFLAG_ 0x40 /*------------------------------------------------ EEAEN (F7h) Bit Register ------------------------------------------------*/ #define EAEN_ 0x01 #define MDSF_ 0x02 /*------------------------------------------------ I2C1SLA (FBh) Bit Register ------------------------------------------------*/ #define SLA1_0_ 0x01 #define SLA1_1_ 0x02 #define SLA1_2_ 0x04 #define SLA1_3_ 0x08 #define SLA1_4_ 0x10 #define SLA1_5_ 0x20 #define SLA1_6_ 0x40 #define SLA1_7_ 0x80 /*------------------------------------------------ I2C1DAT (FCh) Bit Register ------------------------------------------------*/ #define MDAT1_0_ 0x01 #define MDAT1_1_ 0x02 #define MDAT1_2_ 0x04 #define MDAT1_3_ 0x08 #define MDAT1_4_ 0x10 #define MDAT1_5_ 0x20 #define MDAT1_6_ 0x40 #define MDAT1_7_ 0x80 /*------------------------------------------------ Interrupt Vectors: Interrupt Address = (Number * 8) + 3 ------------------------------------------------*/ #define INT0_VECTOR 0 // 0x03 #define TF0_VECTOR 1 // 0x0B #define WDT_VECTOR 2 // 0x13 #define TF1_VECTOR 3 // 0x1B #define I2C0_VECTOR 4 // 0x23 #define I2C1_VECTOR 5 // 0x2B #define LVD_VECTOR 6 // 0x33 #define TSIF_VECTOR 7 // 0x3B /*------------------------------------------------ IAP Call function ------------------------------------------------*/ #define iap_eeprom_program 0xFF0A #define iap_eeprom_erase 0xFF00 /*------------------------------------------------ Register Banks ------------------------------------------------*/ #define REGISTER_BANK_0 0 /* Register Bank 0 */ #define REGISTER_BANK_1 1 /* Register Bank 1 */ #define REGISTER_BANK_2 2 /* Register Bank 2 */ #define REGISTER_BANK_3 3 /* Register Bank 3 */ /*----------------------------------------------*/ #endif