// ************************************************************************** // // This confidential and proprietary Header_file may be used only as // authorised by a licensing agreement from CORERIVER Semiconductor Co., Ltd. // // (c) Copyright 2008 CORERIVER Semiconductor Co., Ltd. // All Rights Reserved // // The entire notice above must be reproduced on all authorised // copies and copies may only be made to the extent permitted // by a licensing agreement from CORERIVER Semiconductor Co., Ltd. // // ----------------------------------------------------------------------- // *** Subject : ADCore.H (ver 0.1) // ----------------------------------------------------------------------- // Header file for the GenCore Turbo ADCore //************************************************************************* #ifndef ADCORE_HEADER_FILE #define ADCORE_HEADER_FILE 1 /*========================================================*/ /*------- Define of Byte Registers ----------------------------------*/ /*========================================================*/ sfr P0 = 0x80; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr ALTSEL = 0x85; sfr CKSEL = 0x86; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr CKCON = 0x8E; sfr RINGCON = 0x8F; sfr P1 = 0x90; sfr EXIF = 0x91; sfr PWM0CON = 0x92; sfr PWM0CNT = 0x93; sfr PWM0D0 = 0x94; sfr PWM0D1 = 0x95; sfr PWM0D2 = 0x96; sfr PWM0D3 = 0x97; sfr SCON = 0x98; sfr SBUF = 0x99; sfr PWM0OEN = 0x9B; sfr PWM0D4 = 0x9C; sfr PWM0D5 = 0x9D; sfr PWM0D6 = 0x9E; sfr PWM0D7 = 0x9F; sfr P2 = 0xA0; sfr EIE = 0xA1; sfr PWM1CON = 0xA2; sfr PWM1CNT = 0xA3; sfr PWM1D0 = 0xA4; sfr PWM1D1 = 0xA5; sfr PWM1D2 = 0xA6; sfr PWM1D3 = 0xA7; sfr IE = 0xA8; sfr SADDR = 0xA9; sfr PWM1OEN = 0xAB; sfr P0HD = 0xAC; sfr P1HD = 0xAD; sfr P2HD = 0xAE; sfr P3HD = 0xAF; sfr P3 = 0xB0; sfr EIP = 0xB1; sfr IT = 0xB2; sfr IPH = 0xB7; sfr IP = 0xB8; sfr SADEN = 0xB9; sfr ITSEL = 0xBA; sfr TSPDM = 0xBB; sfr TSENCTH = 0xBC; sfr TSENCTL = 0xBD; sfr TSPCM = 0xBE; sfr TSPCL = 0xBF; sfr SPIST = 0xC0; sfr TSCON = 0xC1; sfr TSCFG = 0xC2; sfr TSPDH = 0xC3; sfr PMR = 0xC4; sfr STATUS = 0xC5; sfr OSCICN = 0xC6; sfr OSCICN2 = 0xC7; sfr T2CON = 0xC8; sfr T2MOD = 0xC9; sfr RCAP2L = 0xCA; sfr RCAP2H = 0xCB; sfr TL2 = 0xCC; sfr TH2 = 0xCD; sfr ADENB = 0xCE; sfr ADCOSC = 0xCF; sfr PSW = 0xD0; sfr P3SEL = 0xD4; sfr ADCFG = 0xD5; sfr ADCON = 0xD6; sfr ADCSEL = 0xD7; sfr WDCON = 0xD8; sfr P0TYPE = 0xD9; sfr P1TYPE = 0xDA; sfr P2TYPE = 0xDB; sfr P3TYPE = 0xDC; sfr ADRDL = 0xDD; sfr ADRDM = 0xDE; sfr ADRDH = 0xDF; sfr ACC = 0xE0; sfr P0DIR = 0xE1; sfr P1DIR = 0xE2; sfr P2DIR = 0xE3; sfr P3DIR = 0xE4; sfr ADOFL = 0xE5; sfr ADOFM = 0xE6; sfr ADOFH = 0xE7; sfr I2C0ST = 0xE8; sfr I2C0CON = 0xE9; sfr I2C0CFG = 0xEA; sfr I2C0SLA = 0xEB; sfr I2C0DAT = 0xEC; sfr I2C0SCL = 0xED; sfr ADCMD = 0xEF; sfr B = 0xF0; sfr FCNTLD = 0xF1; sfr FCNTL = 0xF2; sfr FCNTM = 0xF3; sfr FCNTH = 0xF4; sfr FCON = 0xF6; sfr FAEN = 0xF7; sfr I2C1ST = 0xF8; sfr I2C1CON = 0xF9; sfr I2C1CFG = 0xFA; sfr I2C1SLA = 0xFB; sfr I2C1DAT = 0xFC; sfr I2C1SCL = 0xFD; /* ------- End of Byte Registers ----------------------------------- */ /*=========================================================*/ /*------- Define of Bit Register ----------------------------------*/ /*=========================================================*/ /*------------------------------------------------ P0 (80h) Bit Register ------------------------------------------------*/ sbit P02 = 0x82; sbit P03 = 0x83; sbit P04 = 0x84; sbit P05 = 0x85; sbit P06 = 0x86; sbit P07 = 0x87; /*------------------------------------------------ TCON (88h) Bit Register ------------------------------------------------*/ sbit IT0 = 0x88; sbit IE0 = 0x89; sbit IT1 = 0x8A; sbit IE1 = 0x8B; sbit TR0 = 0x8C; sbit TF0 = 0x8D; sbit TR1 = 0x8E; sbit TF1 = 0x8F; /*------------------------------------------------ P1 (91h) Bit Register ------------------------------------------------*/ sbit P10 = 0x90; sbit P11 = 0x91; sbit P12 = 0x92; sbit P13 = 0x93; sbit P14 = 0x94; sbit P15 = 0x95; sbit P16 = 0x96; sbit P17 = 0x97; /*------------------------------------------------ SCON (98h) Bit Register ------------------------------------------------*/ sbit RI = 0x98; sbit TI = 0x99; sbit RB8 = 0x9A; sbit TB8 = 0x9B; sbit REN = 0x9C; sbit SM2 = 0x9D; sbit SM1 = 0x9E; sbit SM0 = 0x9F; /*------------------------------------------------ P2 (A0h) Bit Register ------------------------------------------------*/ sbit P21 = 0xA1; sbit P22 = 0xA2; sbit P23 = 0xA3; sbit P24 = 0xA4; sbit P25 = 0xA5; sbit P26 = 0xA6; sbit P27 = 0xA7; /*------------------------------------------------ IE (A8h) Bit Register ------------------------------------------------*/ sbit EX0 = 0xA8; sbit ET0 = 0xA9; sbit EX1 = 0xAA; sbit ET1 = 0xAB; sbit ES = 0xAC; sbit ET2 = 0xAD; sbit EADC = 0xAE; sbit EA = 0xAF; /*------------------------------------------------ P3 (B0h) Bit Register ------------------------------------------------*/ sbit P30 = 0xB0; sbit P31 = 0xB1; sbit P32 = 0xB2; sbit P33 = 0xB3; sbit P34 = 0xB4; /*------------------------------------------------ IP (B8h) Bit Register ------------------------------------------------*/ sbit PX0 = 0xB8; sbit PT0 = 0xB9; sbit PX1 = 0xBA; sbit PT1 = 0xBB; sbit PS = 0xBC; sbit PT2 = 0xBD; sbit PADC = 0xBE; /*------------------------------------------------ T2CON (C8h) Bit Register ------------------------------------------------*/ sbit CP_RL2 = 0xC8; sbit C_T2 = 0xC9; sbit TR2 = 0xCA; sbit EXEN2 = 0xCB; sbit TCLK = 0xCC; sbit RCLK = 0xCD; sbit EXF2 = 0xCE; sbit TF2 = 0xCF; /*------------------------------------------------ PSW (D0h) Bit Register ------------------------------------------------*/ sbit P = 0xD0; sbit F1 = 0xD1; sbit OV = 0xD2; sbit RS0 = 0xD3; sbit RS1 = 0xD4; /* [0,0] : Bank 0 [0,1] : Bank 1 [1,0] : Bank 2 [1,1] : Bank 3*/ sbit F0 = 0xD5; sbit AC = 0xD6; sbit CY = 0xD7; /*------------------------------------------------ WDCON (D8h) Bit Register ------------------------------------------------*/ sbit RWT = 0xD8; sbit EWT = 0xD9; sbit WTRF = 0xDA; sbit WDIF = 0xDB; sbit POR = 0xDE; sbit WDMOD = 0xDF; /*------------------------------------------------ ACC (E0h) Bit Register ------------------------------------------------*/ sbit ACC0 = 0xE0; sbit ACC1 = 0xE1; sbit ACC2 = 0xE2; sbit ACC3 = 0xE3; sbit ACC4 = 0xE4; sbit ACC5 = 0xE5; sbit ACC6 = 0xE6; sbit ACC7 = 0xE7; /*------------------------------------------------ I2CST (E8h) Bit Value ------------------------------------------------*/ sbit I2CBF = 0xE8; sbit I2CS = 0xE9; sbit I2CP = 0xEA; sbit I2CDA = 0xEB; sbit I2CRW = 0xEC; sbit I2CACK = 0xED; sbit I2COF = 0xEE; sbit I2CIF = 0xEF; /*------------------------------------------------ B (F0h) Bit Register ------------------------------------------------*/ sbit B0 = 0xF0; sbit B1 = 0xF1; sbit B2 = 0xF2; sbit B3 = 0xF3; sbit B4 = 0xF4; sbit B5 = 0xF5; sbit B6 = 0xF6; sbit B7 = 0xF7; /*------------------------------------------------ I2C1ST (F8h) Bit Register ------------------------------------------------*/ sbit I2C1BF = 0xF8; sbit I2C1S = 0xF9; sbit I2C1P = 0xFA; sbit I2C1DA = 0xFB; sbit I2C1RW = 0xFC; sbit I2C1ACK = 0xFD; sbit I2C1OF = 0xFE; sbit I2C1IF = 0xFF; /* ------- End of Bit Register ----------------------------------- */ /*==========================================================*/ /*------- Define of Bit Values ----------------------------------*/ /*==========================================================*/ /*------------------------------------------------ P0 (80h) Bit Values ------------------------------------------------*/ #define P0_2_ 0x04 #define P0_3_ 0x08 #define P0_4_ 0x10 #define P0_5_ 0x20 #define P0_6_ 0x40 #define P0_7_ 0x80 /*------------------------------------------------ SP (81h) Bit Values ------------------------------------------------*/ #define SP0_ 0x01 #define SP1_ 0x02 #define SP2_ 0x04 #define SP3_ 0x08 #define SP4_ 0x10 #define SP5_ 0x20 #define SP6_ 0x40 #define SP7_ 0x80 /*------------------------------------------------ DPL (82h) Bit Values ------------------------------------------------*/ #define DPL0_ 0x01 #define DPL1_ 0x02 #define DPL2_ 0x04 #define DPL3_ 0x08 #define DPL4_ 0x10 #define DPL5_ 0x20 #define DPL6_ 0x40 #define DPL7_ 0x80 /*------------------------------------------------ DPH (83h) Bit Values ------------------------------------------------*/ #define DPH0_ 0x01 #define DPH1_ 0x02 #define DPH2_ 0x04 #define DPH3_ 0x08 #define DPH4_ 0x10 #define DPH5_ 0x20 #define DPH6_ 0x40 #define DPH7_ 0x80 /*------------------------------------------------ ALTSEL (85h) Bit Values ------------------------------------------------*/ #define RST_IOEN_ 0x01 #define XTAL_IOEN_ 0x02 #define UART_A_ 0x08 /*------------------------------------------------ CKSEL (86h) Bit Values ------------------------------------------------*/ #define R32KEN_ 0x01 #define RGPR_ 0x02 #define R96MOE_ 0x08 #define R32KOE_ 0x10 /*------------------------------------------------ PCON (87h) Bit Values ------------------------------------------------*/ #define IDL_ 0x01 /* IDLE Mode Bit */ #define PD_ 0x02 /* Power Down Mode Bit */ #define GF0_ 0x04 /* General Purpose Flag */ #define GF1_ 0x08 /* General Purpose Flag */ #define POF_ 0x10 /* Power Off Flag */ #define SMOD0_ 0x40 /* Enable SM0 access. Don¡¯t modify this bit */ #define SMOD1_ 0x80 /* Timer 1 baudrate double in UART mode 1, 2, 3 */ /*------------------------------------------------ TCON (88h)Bit Values ------------------------------------------------*/ #define IT0_ 0x01 #define IE0_ 0x02 #define IT1_ 0x04 #define IE1_ 0x08 #define TR0_ 0x10 #define TF0_ 0x20 #define TR1_ 0x40 #define TF1_ 0x80 /*------------------------------------------------ TMOD (89h) Bit Values ------------------------------------------------*/ #define T0_M0_ 0x01 /* T0_M1, T0_M0 : Timer 0 Mode Select. */ #define T0_M1_ 0x02 #define T0_CT_ 0x04 /* Timer 1 Counter/Timer Select. When Set, COunter by T0 pin. */ #define T0_GATE_ 0x08 /* Timer 1 Gate Control */ #define T1_M0_ 0x10 /* T0_M1, T0_M0 : Timer 1 Mode Select. */ #define T1_M1_ 0x20 #define T1_CT_ 0x40 /* Timer 1 Counter/Timer Select. When Set, COunter by T0 pin. */ #define T1_GATE_ 0x80 /* Timer 1 Gate Control */ /*------------------------------------------------ TL0 (8Ah) Bit Values ------------------------------------------------*/ #define TL0_0_ 0x01 #define TL0_1_ 0x02 #define TL0_2_ 0x04 #define TL0_3_ 0x08 #define TL0_4_ 0x10 #define TL0_5_ 0x20 #define TL0_6_ 0x40 #define TL0_7_ 0x80 /*------------------------------------------------ TL1 (8Bh) Bit Values ------------------------------------------------*/ #define TL1_0_ 0x01 #define TL1_1_ 0x02 #define TL1_2_ 0x04 #define TL1_3_ 0x08 #define TL1_4_ 0x10 #define TL1_5_ 0x20 #define TL1_6_ 0x40 #define TL1_7_ 0x80 /*------------------------------------------------ TH0 (8Ch) Bit Values ------------------------------------------------*/ #define TH0_0_ 0x01 #define TH0_1_ 0x02 #define TH0_2_ 0x04 #define TH0_3_ 0x08 #define TH0_4_ 0x10 #define TH0_5_ 0x20 #define TH0_6_ 0x40 #define TH0_7_ 0x80 /*------------------------------------------------ TH1 (8Dh) Bit Values ------------------------------------------------*/ #define TH1_0_ 0x01 #define TH1_1_ 0x02 #define TH1_2_ 0x04 #define TH1_3_ 0x08 #define TH1_4_ 0x10 #define TH1_5_ 0x20 #define TH1_6_ 0x40 #define TH1_7_ 0x80 /*------------------------------------------------ CKCON (8Eh) Bit Values ------------------------------------------------*/ #define T0M_ 0x04 /* Timer 1 Counter/Timer Select. When Set, COunter by T0 pin. */ #define T1M_ 0x08 /* Timer 1 Gate Control */ #define T2M_ 0x10 /* T0_M1, T0_M0 : Timer 1 Mode Select. */ #define WD0_ 0x20 #define WD1_ 0x40 /* Timer 1 Counter/Timer Select. When Set, COunter by T0 pin. */ #define WD2_ 0x80 /* Timer 1 Gate Control */ /*------------------------------------------------ RINGCON (8Fh) Bit Values ------------------------------------------------*/ #define S0_ 0x01 #define S1_ 0x02 #define S2_ 0x04 #define S3_ 0x08 #define S4_ 0x10 #define S5_ 0x20 #define S6_ 0x40 #define S7_ 0x80 /*------------------------------------------------ P1 (90h) Bit Values ------------------------------------------------*/ #define P1_0_ 0x01 #define P1_1_ 0x02 #define P1_2_ 0x04 #define P1_3_ 0x08 #define P1_4_ 0x10 #define P1_5_ 0x20 #define P1_6_ 0x40 #define P1_7_ 0x80 /*------------------------------------------------ EXIF (91h) Bit Value ------------------------------------------------*/ #define BGS_ 0x01 /* Band-gap Select. When set, LVD will run in power-down mode. */ #define RGSL_ 0x02 /* When wakeup from power down mode in XTAL clock, use RING oscillator as system clock during 65,536 XTAL clocks */ #define RGMD_ 0x04 /* RING mode */ #define XTRG_ 0x08 /* Crystal Select. Read only*/ #define IE3_ 0x20 /* External Interrupt 3 Flag_b */ #define IE4_ 0x40 /* External Interrupt 4 Flag_b */ /*------------------------------------------------ PWM0CON (92h) Bit Register (PWMA CH0 Control Register) PWM1CON (A2h) Bit Register (PWMA CH1 Control Register) ------------------------------------------------*/ #define PWMEN_ 0x01 /* PWMA counter run control bit */ #define PWMOVF_ 0x02 /* PWMA counter overflow flag */ #define CPS0_ 0x10 /* PWMA counter frequency selection */ #define CPS1_ 0x20 #define CPS2_ 0x40 /* [0,0,0] = FOSC / 1 ; Default [0,0,1] = FOSC / 2 [0,1,0] = FOSC / 4 [0,1,1] = FOSC / 8 [1,0,0] = FOSC / 16 [1,0,1] = FOSC / 32 [1,1,0] = FOSC / 64 [1,1,1] = FOSC / 128 */ /*------------------------------------------------ PWM0CNT (93h) Bit Values PWM1CNT (A3h) Bit Values ------------------------------------------------*/ #define CNT0_ 0x01 #define CNT1_ 0x02 #define CNT2_ 0x04 #define CNT3_ 0x08 #define CNT4_ 0x10 #define CNT5_ 0x20 #define CNT6_ 0x40 #define CNT7_ 0x80 /*------------------------------------------------ PWM0D0 (94h) Bit Values PWM0D1 (95h) Bit Values PWM0D2 (96h) Bit Values PWM0D3 (97h) Bit Values PWM0D4 (9Ch) Bit Values PWM0D5 (9Dh) Bit Values PWM0D6 (9Eh) Bit Values PWM0D7 (9Fh) Bit Values PWM1D0 (A4h) Bit Values PWM1D1 (A5h) Bit Values PWM1D2 (A6h) Bit Values PWM1D3 (A7h) Bit Values ------------------------------------------------*/ #define PWMD0 0x01 #define PWMD1_ 0x02 #define PWMD2_ 0x04 #define PWMD3_ 0x08 #define PWMD4_ 0x10 #define PWMD5_ 0x20 #define PWMD6_ 0x40 #define PWMD7_ 0x80 /*------------------------------------------------ SCON(98h) Bit Values ------------------------------------------------*/ #define RI_ 0x01 #define TI_ 0x02 #define RB8_ 0x04 #define TB8_ 0x08 #define REN_ 0x10 #define SM2_ 0x20 #define SM1_ 0x40 #define SM0_ 0x80 /*------------------------------------------------ SBUF (99h) Bit Values ------------------------------------------------*/ #define SBUF0_ 0x01 #define SBUF1_ 0x02 #define SBUF2_ 0x04 #define SBUF3_ 0x08 #define SBUF4_ 0x10 #define SBUF5_ 0x20 #define SBUF6_ 0x40 #define SBUF7_ 0x80 /*------------------------------------------------ P2 (A0h) Bit Values ------------------------------------------------*/ #define P2_1_ 0x02 #define P2_2_ 0x04 #define P2_3_ 0x08 #define P2_4_ 0x10 #define P2_5_ 0x20 #define P2_6_ 0x40 #define P2_7_ 0x80 /*------------------------------------------------ EIE (A1h) Bit Value ------------------------------------------------*/ #define EX3_ 0x02 /* External interrupt 3 enable */ #define EX4_ 0x04 /* External interrupt 4 enable */ #define EWDT_ 0x10 /* Watchdog timer interrupt enable */ #define EI2C0_ 0x20 /* I2C interrupt enable */ #define EI2C1 0x40 /* I2C interrupt enable */ /*------------------------------------------------ PWM0OEN (9Bh) Bit Value (PWMA CH0 Module Output Enable) PWM1OEN (ABh) Bit Value (PWMA CH1 Module Output Enable) ------------------------------------------------*/ #define OE0_ 0x01 /* Module 0 PWM output enable */ #define OE1_ 0x02 /* Module 1 PWM output enable */ #define OE2_ 0x04 /* Module 2 PWM output enable */ #define OE3_ 0x08 /* Module 3 PWM output enable */ #define OE4_ 0x10 /* Module 4 PWM output enable */ #define OE5_ 0x20 /* Module 5 PWM output enable */ #define OE6_ 0x40 /* Module 6 PWM output enable */ #define OE7_ 0x80 /* Module 7 PWM output enable */ /*------------------------------------------------ PWM1CON (A2h) Bit Value ------------------------------------------------*/ #define PWMEN_ 0x01 /* PWMA counter run control bit */ #define PWMOVF_ 0x02 /* PWMA counter overflow flag */ #define CPS0_ 0x10 /* PWMA counter frequency selection */ #define CPS1_ 0x20 /* PWMA counter frequency selection */ #define CPS2_ 0x40 /* PWMA counter frequency selection */ /*------------------------------------------------ IE (A8h) Bit Values ------------------------------------------------*/ #define EX0_ 0x01 #define ET0_ 0x02 #define EX1_ 0x04 #define ET1_ 0x08 #define ES_ 0x10 #define ET2_ 0x20 #define EADC_ 0x40 #define EA_ 0x80 /*------------------------------------------------ SADDR (A9h) Bit Values ------------------------------------------------*/ #define SADDR0_ 0x01 #define SADDR1_ 0x02 #define SADDR2_ 0x04 #define SADDR3_ 0x08 #define SADDR4_ 0x10 #define SADDR5_ 0x20 #define SADDR6_ 0x40 #define SADDR7_ 0x80 /*------------------------------------------------ P0HD (ACh) Bit Values ------------------------------------------------*/ #define P0HD2_ 0x04 #define P0HD3_ 0x08 #define P0HD4_ 0x10 #define P0HD5_ 0x20 #define P0HD6_ 0x40 #define P0HD7_ 0x80 /*------------------------------------------------ P1HD (ADh) Bit Values ------------------------------------------------*/ #define P1HD0_ 0x01 #define P1HD1_ 0x02 #define P1HD2_ 0x04 #define P1HD3_ 0x08 #define P1HD4_ 0x10 #define P1HD5_ 0x20 #define P1HD6_ 0x40 #define P1HD7_ 0x80 /*------------------------------------------------ P2HD (AEh) Bit Values ------------------------------------------------*/ #define P2HD1_ 0x02 #define P2HD2_ 0x04 #define P2HD3_ 0x08 #define P2HD4_ 0x10 #define P2HD5_ 0x20 #define P2HD6_ 0x40 /*------------------------------------------------ P3HD (AFh) Bit Values ------------------------------------------------*/ #define P3HD0_ 0x01 #define P3HD1_ 0x02 /*------------------------------------------------ P3 (B0h) Bit Values ------------------------------------------------*/ #define P3_0_ 0x01 #define P3_1_ 0x02 #define P3_2_ 0x04 #define P3_3_ 0x08 #define P3_4_ 0x10 /*------------------------------------------------ EIP (B1h) Bit Value ------------------------------------------------*/ #define PX3_ 0x02 /* External interrupt 3 priority bit */ #define PX4_ 0x04 /* External interrupt 4 priority bit */ #define PWDT_ 0x10 /* Watchdog timer interrupt priority bit */ #define PI2C0_ 0x20 /* I2C0 interrupt priority bit */ #define PI2C1_ 0x40 /* I2C1 interrupt priority bit */ /*------------------------------------------------ IT (B2h) Bit Value ------------------------------------------------*/ #define IT3_ 0x02 /* Interrupt3 Type Selection Flag */ #define IT4_ 0x04 /* Interrupt4 Type Selection Flag */ /*------------------------------------------------ IPH (B7h) Bit Value ------------------------------------------------*/ #define PX0H_ 0x01 /* External interrupt 0 priority high */ #define PT0H_ 0x02 /* Timer 0 interrupt priority high */ #define PX1H_ 0x04 /* External interrupt 1 priority high */ #define PT1H_ 0x08 /* Timer 1 interrupt priority high */ #define PSH_ 0x10 /* Serial Port (UART) interrupt priority high */ #define PT2H_ 0x20 /* Timer 2 interrupt priority high */ #define PADCH_ 0x40 /* ADC interrupt priority high */ /*------------------------------------------------ IP (B8h) Bit Values ------------------------------------------------*/ #define PX0_ 0x01 #define PT0_ 0x02 #define PX1_ 0x04 #define PT1_ 0x08 #define PS_ 0x10 #define PT2_ 0x20 #define PADC_ 0x40 /*------------------------------------------------ SADEN (B9h) Bit Values ------------------------------------------------*/ #define SADEN0_ 0x01 #define SADEN1_ 0x02 #define SADEN2_ 0x04 #define SADEN3_ 0x08 #define SADEN4_ 0x10 #define SADEN5_ 0x20 #define SADEN6_ 0x40 #define SADEN7_ 0x80 /*------------------------------------------------ ITSEL (BAh) Bit Value ------------------------------------------------*/ #define ITSEL0_ 0x01 /* Interrupt0 Polarity Selection Flag */ /* [0] : low level or negative edge detect [1] : high level or positive edge detect */ #define ITSEL1_ 0x02 /* Interrupt1 Polarity Selection Flag */ #define ITSEL2_ 0x04 /* Interrupt2 Polarity Selection Flag */ #define ITSEL3_ 0x08 /* Interrupt3 Polarity Selection Flag */ #define ITSEL4_ 0x10 /* Interrupt4 Polarity Selection Flag */ /*------------------------------------------------ PMR (C4h) Bit Value ------------------------------------------------*/ #define XTOFF_ 0x08 /* Power Management Control Register */ /*------------------------------------------------ STATUS (C5h) Bit Value ------------------------------------------------*/ #define XTUP_ 0x10 /* Crystal oscillator warm-up status */ /*------------------------------------------------ OSCICN (C6h) Bit Value ------------------------------------------------*/ #define DIV0_ 0x01 /* Ring Oscillator divider */ #define DIV1_ 0x02 #define RINGON_ 0x04 /* 1 = Internal ring Oscillator is running */ #define DIV2_ 0x08 /* Ring Oscillator divider. (FOSC : 96MHz) [0,0,0] = FOSC/48 [0,0,1] = FOSC/24 [0,1,0] = FOSC/12 [0,1,1] = FOSC/8 [1,0,0] = FOSC/6 [1,0,1] = FOSC/4 [1,1,0] = FOSC/2 [1,1,1] = Not supported*/ /*------------------------------------------------ OSCICN2 (C7h) Bit Value ------------------------------------------------*/ #define TRINGON_ 0x04 /*------------------------------------------------ T2CON (C8h)Bit Values ------------------------------------------------*/ #define CPRL2_ 0x01 #define CT2_ 0x02 #define TR2_ 0x04 #define EXEN2_ 0x08 #define TCLK_ 0x10 #define RCLK_ 0x20 #define EXF2_ 0x40 #define TF2_ 0x80 /*------------------------------------------------ T2MOD (C9h) Bit Value ------------------------------------------------*/ #define DCEN_ 0x01 /* Timer 2 down count enable. When set, count down */ #define LINBD_ 0x10 #define LINBG_ 0x20 /*------------------------------------------------ RCAP2L (CAh) Bit Values ------------------------------------------------*/ #define RCAP2L_0_ 0x01 #define RCAP2L_1_ 0x02 #define RCAP2L_2_ 0x04 #define RCAP2L_3_ 0x08 #define RCAP2L_4_ 0x10 #define RCAP2L_5_ 0x20 #define RCAP2L_6_ 0x40 #define RCAP2L_7_ 0x80 /*------------------------------------------------ RCAP2H (CBh) Bit Values ------------------------------------------------*/ #define RCAP2H_0_ 0x01 #define RCAP2H_1_ 0x02 #define RCAP2H_2_ 0x04 #define RCAP2H_3_ 0x08 #define RCAP2H_4_ 0x10 #define RCAP2H_5_ 0x20 #define RCAP2H_6_ 0x40 #define RCAP2H_7_ 0x80 /*------------------------------------------------ TL2 (CCh) Bit Values ------------------------------------------------*/ #define TL2_0_ 0x01 #define TL2_1_ 0x02 #define TL2_2_ 0x04 #define TL2_3_ 0x08 #define TL2_4_ 0x10 #define TL2_5_ 0x20 #define TL2_6_ 0x40 #define TL2_7_ 0x80 /*------------------------------------------------ TH2 (CDh) Bit Values ------------------------------------------------*/ #define TH2_0_ 0x01 #define TH2_1_ 0x02 #define TH2_2_ 0x04 #define TH2_3_ 0x08 #define TH2_4_ 0x10 #define TH2_5_ 0x20 #define TH2_6_ 0x40 #define TH2_7_ 0x80 /*------------------------------------------------ ADENB (CEh) Bit Values ------------------------------------------------*/ #define ADENB0_ 0x01 #define ADENB1_ 0x02 #define ADENB2_ 0x04 #define ADENB3_ 0x08 #define ADENB4_ 0x10 #define ADENB5_ 0x20 #define ADC_IN_FIX_ 0x80 /*------------------------------------------------ ADCOSC (CFh) Bit Values ------------------------------------------------*/ #define ADIV0_ 0x01 #define ADIV1_ 0x02 #define ADIV2_ 0x04 #define ADCLK_EN_ 0x08 #define AD_XTRG_ 0x10 /*------------------------------------------------ PSW (D0h) Bit Values ------------------------------------------------*/ #define P_ 0x01 #define F1_ 0x02 #define OV_ 0x04 #define RS0_ 0x08 #define RS1_ 0x10 #define F0_ 0x20 #define AC_ 0x40 #define CY_ 0x80 /*------------------------------------------------ P3SEL (D4h) Bit Value ------------------------------------------------*/ #define P3SEL0_ 0x01 /* Port 3 Pull-up Control Register */ #define P3SEL1_ 0x02 /* 0 = Pull-up resistor ON (Default) */ #define P3SEL2_ 0x04 /* 1 = Pull-up resistor OFF */ #define P3SEL3_ 0x08 #define P3SEL4_ 0x10 /*------------------------------------------------ ADCFG (D5h) Bit Values ------------------------------------------------*/ #define ADSFT0_ 0x01 #define ADSFT1_ 0x02 #define ADSFT2_ 0x04 #define ADSFT3_ 0x08 #define ADSFT4_ 0x10 #define ADPGA0_ 0x20 #define ADPGA1_ 0x40 #define ADPGA2_ 0x80 /*------------------------------------------------ ADCON (D6h) Bit Values ------------------------------------------------*/ #define ADC_PW_ 0x01 #define ADC_WK_ 0x02 #define ADC_EN_ 0x04 #define ADC_RSTB_ 0x08 #define ADCF_ 0x10 /*------------------------------------------------ ADCSEL (C7h) Bit Values ------------------------------------------------*/ #define ADCS0_ 0x01 #define ADCS1_ 0x02 #define ADCS2_ 0x04 /*------------------------------------------------ WDCON (D8h) Bit Values ------------------------------------------------*/ #define RWT_ 0x01 #define EWT_ 0x02 #define WTRF_ 0x04 #define WDIF_ 0x08 #define POR_ 0x40 #define WDMOD_ 0x80 /*------------------------------------------------ P0TYPE (D9h) Bit Value ------------------------------------------------*/ #define P0TY0_ 0x01 /* Port0 push-pull/open-drain control */ #define P0TY1_ 0x02 /* 0 = Push-pull */ #define P0TY2_ 0x04 /* 1 = Open-drain (Default) */ #define P0TY3_ 0x08 #define P0TY4_ 0x10 #define P0TY5_ 0x20 #define P0TY6_ 0x40 #define P0TY7_ 0x80 /*------------------------------------------------ P1TYPE (DAh) Bit Value ------------------------------------------------*/ #define P1TY0_ 0x01 /* Port1 push-pull/open-drain control */ #define P1TY1_ 0x02 /* 0 = Push-pull */ #define P1TY2_ 0x04 /* 1 = Open-drain (Default) */ #define P1TY3_ 0x08 #define P1TY4_ 0x10 #define P1TY5_ 0x20 #define P1TY6_ 0x40 #define P1TY7_ 0x80 /*------------------------------------------------ P2TYPE (DBh) Bit Value ------------------------------------------------*/ #define P2TY0_ 0x01 /* Port2 push-pull/open-drain control */ #define P2TY1_ 0x02 /* 0 = Push-pull */ #define P2TY2_ 0x04 /* 1 = Open-drain (Default) */ #define P2TY3_ 0x08 #define P2TY4_ 0x10 #define P2TY5_ 0x20 #define P2TY6_ 0x40 #define P2TY7_ 0x80 /*------------------------------------------------ P3TYPE (DCh) Bit Value ------------------------------------------------*/ #define P3TY0_ 0x01 /* Port3 push-pull/open-drain control */ #define P3TY1_ 0x02 /* 0 = Push-pull */ #define P3TY2_ 0x04 /* 1 = Open-drain (Default) */ #define P3TY3_ 0x08 #define P3TY4_ 0x10 /*------------------------------------------------ ADRDL (DDh) Bit Value ------------------------------------------------*/ #define ADRD0_ 0x01 #define ADRD1_ 0x02 #define ADRD2_ 0x04 #define ADRD3_ 0x08 #define ADRD4_ 0x10 #define ADRD5_ 0x20 #define ADRD6_ 0x40 #define ADRD7_ 0x80 /*------------------------------------------------ ADRDM (DEh) Bit Value ------------------------------------------------*/ #define ADRD8_ 0x01 #define ADRD9_ 0x02 #define ADRD10_ 0x04 #define ADRD11_ 0x08 #define ADRD12_ 0x10 #define ADRD13_ 0x20 #define ADRD14_ 0x40 #define ADRD15_ 0x80 /*------------------------------------------------ ADRDH (DFh) Bit Value ------------------------------------------------*/ #define ADRD16_ 0x01 #define ADRD17_ 0x02 #define ADRD18_ 0x04 #define ADRD19_ 0x08 #define ADRD20_ 0x10 #define ADRD21_ 0x20 #define ADRD22_ 0x40 #define ADRD23_ 0x80 /*------------------------------------------------ ACC (E0h)Bit Values ------------------------------------------------*/ #define ACC0_ 0x01 #define ACC1_ 0x02 #define ACC2_ 0x04 #define ACC3_ 0x08 #define ACC4_ 0x10 #define ACC5_ 0x20 #define ACC6_ 0x40 #define ACC7_ 0x80 /*------------------------------------------------ P0DIR (E1h) Bit Value ------------------------------------------------*/ #define P0DIR2_ 0x04 #define P0DIR3_ 0x08 #define P0DIR4_ 0x10 #define P0DIR5_ 0x20 #define P0DIR6_ 0x40 #define P0DIR7_ 0x80 /*------------------------------------------------ P1DIR (E2h) Bit Value ------------------------------------------------*/ #define P1DIR0_ 0x01 #define P1DIR1_ 0x02 #define P1DIR2_ 0x04 #define P1DIR3_ 0x08 #define P1DIR4_ 0x10 #define P1DIR5_ 0x20 #define P1DIR6_ 0x40 #define P1DIR7_ 0x80 /*------------------------------------------------ P2DIR (E3h) Bit Value ------------------------------------------------*/ #define P2DIR1_ 0x02 #define P2DIR2_ 0x04 #define P2DIR3_ 0x08 #define P2DIR4_ 0x10 #define P2DIR5_ 0x20 #define P2DIR6_ 0x40 #define P2DIR7_ 0x80 /*------------------------------------------------ P3DIR (E4h) Bit Value ------------------------------------------------*/ #define P3DIR0_ 0x01 #define P3DIR1_ 0x02 #define P3DIR3_ 0x08 #define P3DIR4_ 0x10 /*------------------------------------------------ ADOFL (E5h)Bit Values ------------------------------------------------*/ #define OFFS0_ 0x01 #define OFFS1_ 0x02 #define OFFS2_ 0x04 #define OFFS3_ 0x08 #define OFFS4_ 0x10 #define OFFS5_ 0x20 #define OFFS6_ 0x40 #define OFFS7_ 0x80 /*------------------------------------------------ ADOFM (E6h)Bit Values ------------------------------------------------*/ #define OFFS8_ 0x01 #define OFFS9_ 0x02 #define OFFS10_ 0x04 #define OFFS11_ 0x08 #define OFFS12_ 0x10 #define OFFS13_ 0x20 #define OFFS14_ 0x40 #define OFFS15_ 0x80 /*------------------------------------------------ ADOFH (E7h)Bit Values ------------------------------------------------*/ #define OFFS16_ 0x01 #define OFFS17_ 0x02 #define OFFS18_ 0x04 #define OFFS19_ 0x08 #define OFFS20_ 0x10 #define OFFS21_ 0x20 #define OFFS22_ 0x40 #define OFFS23_ 0x80 /*------------------------------------------------ I2C0ST (E8h) Bit Values ------------------------------------------------*/ #define I2C0BF_ 0x01 #define I2C0S_ 0x02 #define I2C0P_ 0x04 #define I2C0DA_ 0x08 #define I2C0RW_ 0x10 #define I2C0ACK_ 0x20 #define I2C0OF_ 0x40 #define I2C0IF_ 0x80 /*------------------------------------------------ I2C0CON (E9h) Bit Values ------------------------------------------------*/ #define I2CEN_ 0x01 #define I2CIOEN_ 0x02 #define SGEN_ 0x04 #define PGEN_ 0x08 #define LASTB_ 0x10 #define SCLHD_ 0x20 #define SLA2ME_ 0x40 /*------------------------------------------------ I2C0CFG (EAh) Bit Values ------------------------------------------------*/ #define GCE_ 0x01 #define SP_IE_ 0x02 #define ADSEL_ 0x04 #define MSSEL_ 0x08 /*------------------------------------------------ I2C0SLA (EBh) Bit Values ------------------------------------------------*/ #define SLA1_0_ 0x01 #define SLA1_1_ 0x02 #define SLA1_2_ 0x04 #define SLA1_3_ 0x08 #define SLA1_4_ 0x10 #define SLA1_5_ 0x20 #define SLA1_6_ 0x40 #define SLA1_7_ 0x80 /*------------------------------------------------ I2C0DAT (ECh) Bit Values ------------------------------------------------*/ #define DATA0_ 0x01 #define DATA1_ 0x02 #define DATA2_ 0x04 #define DATA3_ 0x08 #define DATA4_ 0x10 #define DATA5_ 0x20 #define DATA6_ 0x40 #define DATA7_ 0x80 /*------------------------------------------------ I2C0SCL (EDh) Bit Values ------------------------------------------------*/ #define MSCL0_ 0x01 #define MSCL1_ 0x02 #define MSCL2_ 0x04 #define MSCL3_ 0x08 #define MSCL4_ 0x10 #define MSCL5_ 0x20 #define MSCL6_ 0x40 #define MSCL7_ 0x80 /*------------------------------------------------ ADCMD (EFh) Bit Values ------------------------------------------------*/ #define ADC_MD_ 0x01 #define ADC_XEN_ 0x02 /*------------------------------------------------ B (F0h) Bit Values ------------------------------------------------*/ #define B0_ 0x01 #define B1_ 0x02 #define B2_ 0x04 #define B3_ 0x08 #define B4_ 0x10 #define B5_ 0x20 #define B6_ 0x40 #define B7_ 0x80 /*------------------------------------------------ FCNTLD (F1h) Bit Value ------------------------------------------------*/ #define FCNTLD_ 0x80; /* EEPROM Erase/Program Time Count Loading */ /*------------------------------------------------ FCNTL (F2h) Bit Values ------------------------------------------------*/ #define FCNT0_ 0x01 #define FCNT1_ 0x02 #define FCNT2_ 0x04 #define FCNT3_ 0x08 #define FCNT4_ 0x10 #define FCNT5_ 0x20 #define FCNT6_ 0x40 #define FCNT7_ 0x80 /*------------------------------------------------ FCNTM (F3h) Bit Values ------------------------------------------------*/ #define FCNT8_ 0x01 #define FCNT9_ 0x02 #define FCNT10_ 0x04 #define FCNT11_ 0x08 #define FCNT12_ 0x10 #define FCNT13_ 0x20 #define FCNT14_ 0x40 #define FCNT15_ 0x80 /*------------------------------------------------ FCNTH (F4h) Bit Values ------------------------------------------------*/ #define FCNT16_ 0x01 #define FCNT17_ 0x02 #define FCNT18_ 0x04 #define FCNT19_ 0x08 #define FCNT20_ 0x10 #define FCNT21_ 0x20 #define FCNT22_ 0x40 #define FCNT23_ 0x80 /*------------------------------------------------ FCON (F6h) Bit Values ------------------------------------------------*/ #define FPGM_ 0x01 #define FSERA_ 0x02 #define FMASE_ 0x04 #define FFLAG_ 0x08 #define IFLAG_ 0x10 /*------------------------------------------------ FAEN (F7h) Bit Values ------------------------------------------------*/ #define FAEN_ 0x01 #define MDSF_ 0x02 /*------------------------------------------------ I2C1ST (F8h) Bit Values ------------------------------------------------*/ #define I2C1BF_ 0x01 #define I2C1S_ 0x02 #define I2C1P_ 0x04 #define I2C1DA_ 0x08 #define I2C1RW_ 0x10 #define I2C1ACK_ 0x20 #define I2C1OF_ 0x40 #define I2C1IF_ 0x80 /*------------------------------------------------ I2C1CON (F9h) Bit Values ------------------------------------------------*/ #define I2CEN_ 0x01 #define I2CIOEN_ 0x02 #define SGEN_ 0x04 #define PGEN_ 0x08 #define LASTB_ 0x10 #define SCLHD_ 0x20 #define SLA2ME_ 0x40 /*------------------------------------------------ I2C1CFG (FAh) Bit Values ------------------------------------------------*/ #define GCE_ 0x01 #define SP_IE_ 0x02 #define ADSEL_ 0x04 /*------------------------------------------------ I2C1SLA (FBh) Bit Values ------------------------------------------------*/ #define SLA1_0_ 0x01 #define SLA1_1_ 0x02 #define SLA1_2_ 0x04 #define SLA1_3_ 0x08 #define SLA1_4_ 0x10 #define SLA1_5_ 0x20 #define SLA1_6_ 0x40 #define SLA1_7_ 0x80 /*------------------------------------------------ I2C1DAT (FCh) Bit Values ------------------------------------------------*/ #define DATA0_ 0x01 #define DATA1_ 0x02 #define DATA2_ 0x04 #define DATA3_ 0x08 #define DATA4_ 0x10 #define DATA5_ 0x20 #define DATA6_ 0x40 #define DATA7_ 0x80 /*------------------------------------------------ I2C1SCL (FDh) Bit Values ------------------------------------------------*/ #define MSCL0_ 0x01 #define MSCL1_ 0x02 #define MSCL2_ 0x04 #define MSCL3_ 0x08 #define MSCL4_ 0x10 #define MSCL5_ 0x20 #define MSCL6_ 0x40 #define MSCL7_ 0x80 /* ------- End of Bit Values -------------------------------------- */ /*========================================================*/ /*------- Define of Interrupt Vectors & Register Banks -----------------*/ /*========================================================*/ /*------------------------------------------------ Interrupt Vectors: Interrupt Address = (Number * 8) + 3 ------------------------------------------------*/ #define INT0_VECTOR 0 /* 0x03 External Interrupt 0 */ #define TF0_VECTOR 1 /* 0x0B Timer 0 */ #define INT1_VECTOR 2 /* 0x13 External Interrupt 1 */ #define TF1_VECTOR 3 /* 0x1B Timer 1 */ #define RITI_VECTOR 4 /* 0x23 Serial Port */ #define TF2_VECTOR 5 /* 0x2B Timer 2 */ #define LVD_VECTOR 6 /* 0x33 LVD */ #define ADC_VECTOR 7 /* 0x3B ADC */ #define INT3_VECTOR 9 /* 0x4B External Interrupt 3 */ #define INT4_VECTOR 10 /* 0x53 External Interrupt 4 */ #define WDT_VECTOR 12 /* 0x63 WDT Interrupt */ #define I2C0_VECTOR 13 /* 0x6B I2C1 Interrupt */ #define I2C1_VECTOR 14 /* 0x73 I2C1 Interrupt */ /*------------------------------------------------ Register Banks ------------------------------------------------*/ #define REGISTER_BANK_0 0 /* Register Bank 0 */ #define REGISTER_BANK_1 1 /* Register Bank 1 */ #define REGISTER_BANK_2 2 /* Register Bank 2 */ #define REGISTER_BANK_3 3 /* Register Bank 3 */ /*----------------------------------------------*/ /* ------- End of Interrupt Vectors & Register Banks ------------ */ #endif